Recently, there has been increased interest in techniques for recrystallizing thin layers of semiconductor, especially silicon, on a buried noncrystalline insulator layer. This technology is generally referred to as silicon-on-insulator (SOI) technology.
SOI technology offers the promise of, inter alia, improved device isolation, reduced junction and parasitic capacitance, and of improved radiation hardness. The method of forming a monocrystalline layer of Si on a layer of SiO.sub.2 that is of interest herein will be referred to as the melting/recrystallization (MR) method. See, for instance, H. W. Lam et al, in VLSI Electronics: Microstructure Science, Vol. 4, N. G. Einspruch, editor, Academic Press (1982), pp. 1-54.
In the MR method, typically a layer of SiO.sub.2 is formed on a single crystal Si substrate, is optionally patterned, a layer of poly-Si is deposited thereover, the poly-Si layer is melted in whole or in part, and one or more solidification fronts are caused to advance laterally across the poly-Si layer. See, for instance, U.S. Pat. No. 4,323,417, issued Apr. 6, 1982, to H. W. Lam.
Various heat sources have been used in the MR method, including strip heaters, electron or laser beams, and tungsten halogen lamps or other sources of high-intensity noncoherent radiation. Various variants of the MR method are known to the art. Among the techniques is a global melting approach, typically comprising simultaneous exposure of a whole wafer to high intensity visible and infrared radiation (G. K. Celler et al, in Laser-Solid Interactions and Transient Thermal Processing of Materials, J. Narayan et al, editors, North Holland, N.Y. (1983), pp. 575-580). A different technique comprises zone melting, i.e., the relatively slow scan of a strip-like hot zone across the sample. The sample, e.g., a wafer, is typically coupled to a heat source that maintains the sample at a temperature several hundred .degree.C. below the melting temperature of the semiconductor material, and the strip-like hot zone (in which the semiconductor material is molten) is scanned across the sample. A variety of means exists for producing the moving hot zone, e.g., a line-focused laser or other light source, or an electron beam. Graphite strip heaters are also used in the prior art. See, for instance, the Fan patent or M. W. Geis et al, Journal of the Electrochemical Society: Solid State Science and Technology, Vol. 129(12), pp. 2812-2818 (1982).
Typically, a capping layer is formed atop the deposited poly-Si to prevent agglomeration and evaporation of the molten Si. The capping layer typically comprises an oxide, e.g., SiO.sub.2. See U.S. Pat. No. 4,371,421, issued Feb. 1, 1983, to J. C. C. Fan et al (Fan). It has been found, however, that the presence of a bare SiO.sub.2 capping layer cannot reliably prevent balling of the molten portion of the poly-Si layer. Improvement has been achieved by coating the SiO.sub.2 capping layer with a Si-rich SiN.sub.x film deposited by sputtering of a Si.sub.3 N.sub.4 target, with nitrogen diffusing through the cap layer to the Si/SiO.sub.2 interface where it promotes wetting. Although capable of producing recrystallized Si films of relatively high quality, wetting was found to be not reliable, with film agglomeration, void formation, and thickness variation occurring with unacceptably high frequency.
A capping technique which was said to have greater reproducibility was disclosed by C. K. Chen et al, Applied Physics Letters, Vol. 48(19), pp. 1300-1302 (1986). These workers reported that annealing of a Si/SiO.sub.2 /0.5 .mu.m poly-Si/SiO.sub.2 sandwich at 1100.degree. C. for 3 hours in NH.sub.3, oxidizing for about 20 minutes in O.sub.2, and annealing in NH.sub.3 for an additional 3 hours results in a cap that is wetted well by the molten poly-Si. The reference reports also that the above treatment results in the presence of a small amount of nitrogen (N) at the poly-Si/cap SiO.sub.2 interface, and that the interfacial N promotes wetting of the molten Si during MR. For thicker (1 .mu.m) poly-Si films a single 8 hours NH.sub.3 anneal was reported to be also effective.
Despite the fact that incorporation of N by the above prior art annealing method improves the reliability of wetting, it has been found that thus produced recrystallized thin Si layers frequently still contain imperfections that limit their usefulness as device material. In particular, recrystallized Si layers have been found to frequently have substantial surface roughness, especially if the melt parameters are not closely controlled. A Si layer comprising such rough surface areas frequently would not be acceptable as device material. Furthermore, as is apparent from the above discussion, prior art techniques for introducing interfacial N require lengthy heat treatment at elevated temperature, and may result in the introduction of N, a donor element, into the recrystallized Si, thereby changing the conduction characteristics of the Si.
In view of the potential significance of SOI devices, availability of a reliable MR method that can result in formation of device quality Si on SiO.sub.2 and that is not subject to some or all of the above discussed shortcomings of the prior art would be desirable. This application discloses such a method.